PFCs are increasingly widely used in power management, for applications ranging from PCs, to adapters and lighting. In order to achieve control of the output voltage, conventionally an error amplifier is used. As will be described in the more detail hereinbelow, the error between the actual output DC voltage and the nominal required DC voltage is amplified and integrated, and the resulting signal is used to adjust the switch-on time of the power switch in the power factor controller. The integration time constant is typically large, in order to avoid instability in the system.
Such a conventional error feedback mechanism can provide an accurate steady-state value of the output voltage. However, the long integration time constant results in a slow response to transient variation of the load current, which slow transient response is not ideal.
European patent application publication EP-A-0,580,237 discloses a power factor correction circuit, with an improved error feedback circuit, in which a sampling-and-hold circuit is series-connected to a conventional error amplifier, in order to improve the transient response. However, for accurate DC output voltage, it is necessary that the sampling occurs at an instant within the mains half-cycle at which the PFC output voltage is equal to the DC value in steady-state; that is to say either during a zero-crossing of the mains or at the mains peak voltage. Thus, this error feedback system is inflexible, in particular since it requires precise detection of the phase of the mains voltage.